This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.