In one embodiment, a digital signal processor includes look ahead logic to
decrease the number of bubbles inserted in the processing pipeline. The
processor receives data containing instructions in a plurality of buffers
and decodes the size of a first instruction. The beginning of a second
instruction is determined based on the size of the first instruction. The
size of the second instruction is decoded and the processor determines
whether loading the second instruction will deplete one of the plurality
of buffers.