A method for modifying an IC layout using a library of pretabulated
models, each model containing an environment with a feature, one or more
geometries, and a modification to the feature that us calculated to
produce a satisfactory feature on a wafer. The model may also contain a
simulation of the environment reflecting no processing variations and/or
a re-simulation of the environment reflecting one or more processing
variations. The model may also contain data describing an electrical
characteristic of the environment as a function of one or more process
variations and/or describing an adjustment equation that uses geometry
coverage percentages of particular areas in the layout to determine an
adjustment to the modification. In some embodiments, and upper layer for
an upper layer of an IC are modified using information (such as a density
map) relating to a lower layout for a lower layer of the IC.