A chip stack includes a field programmable gate array (FPGA) and an
auxiliary component coupled to the FPGA with intercommunicated clock,
control and/or data signals. The auxiliary component has a functionality
mapped into the FPGA. The pin definition of the FPGA is redefined so that
the FPGA and the auxiliary component in combination operate as a modified
FPGA. A test circuit is programmed into the FPGA to exercise the
auxiliary component to test functionality and timing performance at full
speed. The functionality of the auxiliary component mapped into the FPGA
is parameterized, such as for the data word width for reading and/or
writing data words of different lengths into the auxiliary component in
both an aligned and nonaligned manner. A memory interface allows multiple
auxiliary circuits to be accessed through the FPGA either together to
generate a wider data word or serially to achieve a greater memory depth.