An A/D converter includes at least one comparator array (COMP1 COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1 SW7) provide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1 DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1 DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.