Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit assembly, e.g., forming multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the multilayer metal lines, then oxidized. An insulator is deposited to fill interstices created by air gaps between the multilayer metal lines. In one embodiment, forming multilayer metal lines includes a conductor bridge level. In one embodiment, forming a silicide layer on the multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300-500 degrees Celsius. In one embodiment, a metal layer is formed on the oxided silicide layer. The metal layer includes one of Aluminum, Chromium, Titanium, Zirconium and Aluminum oxide.