A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.