A processor having a cache memory structure which improves an operation speed of the processor and a method of managing cache memory of the processor are provided. The cache memory is divided into a cache memory for normal programs which stores instructions required for running normal programs and a cache memory for exception programs. An instruction register fetches and stores instructions from one of the cache memories according to the type of program currently running. The method includes dividing the cache memory into a cache memory for normal programs and a cache memory for exception programs, storing instructions and/or data for running the normal and exception programs in their respective cache memories, determining a type of a currently running program, fetching instructions from either cache memory according to the type of program currently running, and inputting the fetched instructions to the instruction register.