A limited output address register technique for selectively variable write
latency in double data rate 2 (DDR2) integrated circuit memory devices
providing a reduced number of paths directly connected to the output. A
chain of DQ flip-flops is disclosed which is only loaded on valid write
address commands but shifts continually thereafter every clock cycle.
Since new READ or WRITE commands cannot be issued on successive cycles,
at any given point in the chain an address (or state) is valid for at
least two cycles. Therefore, a selected point in the register chain can
be used to satisfy the requirements for two different latencies. For
DDR2, having N write latency cases, only ceil(N/2) access points to the
write address output have to be provided thereby saving on-chip area and
increasing speed. In a specific embodiment disclosed, DDR1 may also be
supported.