A method and a system for scheduling a software pipelined loop with indirect loads. The system may include a data structure in communication with a processor and a memory. The processor may determine a condition associated with a potential for saturation of the data structure. Accordingly, the processor may provide a number of instructions associated with the software pipelined loop from the memory to a queue of the data structure prior to processing of the instructions by the processor based on the condition associated with a potential for saturation of the data structure.