A semiconductor substrate having an upper layer and an alignment mark structure formed on a surface region of the upper layer, the surface region defined by opposite first and second parallel sides extending along the upper layer, outer side walls extending upwardly from the upper layer and extending lengthwise along the side, and are defined lengthwise by alternating first and second wall portions, each of the first wall portions is spaced farther from the first side of the surface region than is each of the second wall portions, and an alignment pattern defined by openings in the alignment mark structure.

 
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< Electrical assembly with internal memory circuitized substrate having electronic components positioned thereon, method of making same, and information handling system utilizing same

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> Frequency measuring device, polishing device using the same and eddy current sensor

> Direct non contact measurement

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