A method of controlling access to a model specific register of a microprocessor.
A method of controlling access to a model specific register of a processor having
a normal execution mode and a secure execution mode may include storing processor
state and mode information in the model specific register. Further, the method
may include protection logic allowing a software invoked write access to modify
the information within the model specific register during the normal execution
mode. The method may further include security logic selectively inhibiting the
software invoked write access during the secure execution mode.