A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

 
Web www.patentalert.com

< Semiconductor chip package

< Single damascene integration scheme for preventing copper contamination of dielectric layer

> Connector for measuring electric resistance, apparatus and method for measuring electric resistance of circuit board

> Contactor having conductive particles in a hole as a contact electrode

~ 00259