A computer bus system comprises: a direct address bus; at least one bus master device and at least one bus slave device, the bus master device and bus slave device being connected to the bus so that the bus master device may communicate with the bus slave device over the bus. The bus has an address space assigned to different devices connected to the bus and is a multiplexed address/data bus for transferring blocks of data (63,76) in a direct address transaction (60) between the devices. Each direct address transaction (60) comprises a burst transaction (61) having an address phase (12,62) with a bus space address value (62) followed by a data phase (63). The bus slave device includes an indirect address device addressable in an indirect address transaction (70) that has an address register load transaction (71) followed by a data register load transaction (72). The indirect address device has a memory with memory locations identified by address values loaded into the address register of the indirect address device. The slave device includes a transaction translation device between the bus and the indirect address device that translates the direct address transaction (61) to an indirect address transaction (70) including mapping (64) the bus space address value (62) to the destination address value (74). Therefore, a direct address transaction (60) received by the slave device for communicated blocks of data is presented to the indirect address device as an indirect address transaction (70).