A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T₀₀ to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock, If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.