A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

 
Web www.patentalert.com

< Disc cartridge including an inner shell formed by severing a molded portion and a flanged thin-walled section

< Application program interface that enables communication for a network software platform

> Spinal fixation apparatus and method

> Cyclic redundancy check (CRC) parity check system and method

~ 00254