An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

 
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> Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching

> Apparatus for controlling multi-word stack operations using a multi-bank stack in digital data processors

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