A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

 
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