Field programmable gate arrays (FPGA's) may be structured in accordance with
the disclosure to have a register-intensive architecture that provides, for each
of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a
logic block, a plurality of in-block accessible registers. A register-feeding multiplexer
means may be provided for allowing each of the plural registers to equivalently
capture and store a result signal output by the corresponding, base LUT of the
plural registers. Registerable, primary and secondary feedthroughs may be provided
for each base LUT so that locally-acquired input signals of the LUT may be fed-through
to the corresponding, in-block registers for register-recovery purposes without
fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage,
input switch matrix (ISM) may be further provided for acquiring and routing input
signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect
lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs.
Techniques are disclosed for utilizing the many in-block registers and/or the registerable
feedthroughs and/or the multi-stage ISM's for efficiently implementing various
circuit designs by appropriately configuring such register-intensive FPGA's.