Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.