A semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.