A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.

 
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