A memory array is divided into a plurality of memory cell blocks in m rows and n columns. A write digit line for each of the memory cell blocks is independent of those for the other memory cell blocks, and is divided corresponding to the memory cell rows. Each write digit line is selectively activated in accordance with information transmitted through a main word line and a segment decode line arranged hierarchically with respect to write digit line and commonly to a plurality of sub-blocks neighboring in the row direction. A data write current in the row direction is supplied only by the write digit line corresponding to the selected memory cell so that erroneous data writing into unselected memory cells can be suppressed.

 
Web www.patentalert.com

< Magneto-resistance effect element, magnetic memory and magnetic head

< Magnetic random access memory

> Method of manufacturing semiconductor device, integrated circuit, electro-optical device, and electronic apparatus

> Magnetic memory cell with plural read transistors

~ 00239