An interface circuit includes a frequency divider which divides a frequency of
a base clock to provide frequency-divided clock signals; a first address register
which stores an address signal at a timing in which the frequency-divided clock
signal is turned to high; a second address register which stores the address signal
at a timing in which the clock signal is turned to low; a first data register which
stores a data signal at a timing in which the clock signal is turned to high; and
a second data register which stores the data signal at a timing in which the clock
signal is turned to low. The data signals stored in the first and second data registers
are selectively outputted.