A signal-processing circuit in which two-stage equalization is performed by using first and second equalization circuits provided on upstream and downstream sides from a phase-locked loop circuit, respectively, the first equalization circuit on the upstream side including a transversal filter to minimize an equalization error caused by the first equalization circuit and to stabilize the operation of the phase-locked loop circuit. Another signal-processing circuit including an analog-to-digital converter and a digital phase-locked loop circuit for receiving the output from the analog-to-digital converter and a recording and playback apparatus using the output are also provided, wherein the output from the analog-to-digital converter is input as the digital signal in the digital phase-locked loop circuit to fetch a detection point voltage and to stabilize the phase-locked loop circuit without an analog circuit.