A verilog-HDL source at the register-transfer level (RTL) is converted into a
programming
language executable on computer. Constructed in an analyzing of elements is a data
structure corresponding to the elements of the verilog-HDL source. Created in an
analyzing of a data-flow are a first data flow from a state register and a second
flow from data-path register. Reconstructed in a reconstructing of a control-structure
is the first data flow. Reconstructed in a reconstructing of a data-path is the
second data flow so that the reconstructed second data is constituted only by circuitry
operating in each state of the control structure. Each reconstructed data flow
is mapped in each state of the control structure in a combining of the control-structure/data-flow,
to output an behavior-level intermediate language. The intermediate language is
converted into a programming language in a generating of an object-code.