A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.