A microprocessor with an apparatus for alleviating the need to maintain coherency
between cache line status of a store buffer and a response buffer each storing
the same cache line address is disclosed. The store buffers include match bits.
When a store operation requires a response buffer to be allocated (e.g., to receive
a cache line implicated by a store miss of a write-allocate cache or to obtain
exclusive ownership of a shared cache line hitting in the cache), control logic
populates the match bits to specify which of the response buffers was allocated.
Control logic updates the cache line status in the allocated response buffer as
status-altering events occur, which is subsequently used to update the cache, thereby
alleviating the need for the store buffer to maintain the cache line status. If
the store address matches an already-allocated response buffer, that response buffer
is specified in the match bits.