A power semiconductor device including a semiconductor die having electrically active first and second surfaces. A mark is located on the second surface configured to facilitate identification of the device and a metal layer is formed over the second surface of the semiconductor die and over the mark. The metal layer is configured to conduct a current of the device and to allow the mark to be visible for identification purposes.

 
Web www.patentalert.com

< Method of forming a stacked device filler

< Semiconductor device with improved reliability and manufacturing method of the same

> Bumped chip carrier package using lead frame and method for manufacturing the same

> Semiconductor device having densely stacked semiconductor chips

~ 00230