A processor chip with a high speed memory cloner that enables movement of data
directly from one memory location (of a data processing system) to another without
the data having to be routed through the processor. The memory cloner includes
processing logic that enables the release of the processor to continue processing
other operations while the data are physically moved in the background. The memory
cloner generates a sequence of naked writes (i.e., write operations with no data
tenure) from the write data commands and forwards the naked writes to the memory
controller of the destination memory module. When all the naked write operations
receive a Null response (i.e., a response indicating that the specific addressed
at the memory module are reserved/set to receive data), the memory cloner signals
the processor that the move request is completed. The memory cloner also comprises
a source and a destination address buffer and a count register, within which are
stored the source and destination addresses and the number of bytes of data to
be moved.