A register address generation tool is used during the design of semiconductor
products.
For those registers and/or memories that are addressable on a bus, the register
address generation tool creates the interconnect RTL, header files, static timing
analysis constraint files, and verification testcases. The tool also maintains
coherence between what has been generated and the available resources for the design
of the semiconductor product in a design. If there are any registers and/or memories
that are not being used, the register address generation tool may further generate
the RTL that will convert these unused resources to performance-enhancing features
such as control registers, status registers, etc. The register address generation
tool read a design database having an application set to determine what hardmacs
and what transistor fabric is available. It also receives as input a bus specification
and address parameters. The register address generation tool may be used with a
suite of generation tools to achieve the rapid design and realization of a new
semiconductor product.