Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same integrated circuit. The microcode unit may be configured to receive a microcoded instruction and to identify a microcode routine that corresponds to the microcoded instruction. The microcode ROMs may collectively store the microcode routines that implement the microcoded instructions of a complex instruction set, and different microcode ROMs may have different access times. At least one of the microcode ROMs may output operations included in the microcode routine in response to the microcode unit identifying the microcode routine. Microcode routines having more performance criticality may be stored in a microcode ROM having a smaller access latency than the access latency of a microcode ROM in which microcode routines having less performance criticality are stored.