A power and power management signaling circuit in a network interface card (NIC) for all known Wake On LAN PCI bus configurations includes a single voltage regulator together with connections to a network-initiated power management recovery signal MPT_—PMEN from the network interface, power management recovery and auxiliary power signals PME_—N and AUX3V within the PCI bus, and a system motherboard header. A first inverter inverts MPT_—PMEN to the PME signal for the header, while a second inverter gates auxiliary power AUXVDD to main power PCIVDD for the NIC when the PCI system power PCI5V is asserted. Diodes prevent back powering of the PCI bus during hibernate states, system power short circuiting and leakage malfunctions when the header is incorrectly connected or unconnected, and auxiliary power shorts to ground when the previously undefined AUX3V PCI bus line is grounded.