A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.