A computer system and a method used to access data from a plurality of memory
devices
with a memory hub. The computer system includes a plurality of memory modules coupled
to a memory hub controller. Each of the memory modules includes the memory hub
and the plurality of memory devices. The memory hub includes a sequencer and a
bypass circuit. When the memory hub is busy servicing one or more memory requests,
the sequencer generates and couples the memory requests to the memory devices.
When the memory hub is not busy servicing multiple memory requests, the bypass
circuit generates and couples a portion of each the memory requests to the memory
devices and the sequencer generates and couples the remaining portion of each of
the memory requests to the memory devices.