Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique

   
   

A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.

 
Web www.patentalert.com

< Fabrication of copper-containing region such as electrical interconnect

< Solder pads and method of making a solder pad

> Semiconductor device and method of manufacturing same

> Planar transformer and output inductor structure with single planar winding board and two magnetic cores

~ 00199