One embodiment of the present invention provides a system that applies resolution
enhancement techniques (RETs) selectively to a layout of an integrated circuit.
Upon receiving the layout of the integrated circuit, the system identifies a plurality
of critical regions within the layout based on an analysis of one or more of, timing,
dynamic power, and off-state leakage current. The system then performs a first
set of aggressive RET operations on the plurality of critical regions. The system
also performs a second set of less aggressive RET operations on other non-critical
regions of the layout.
