JFET and MESFET structures, and processes of making same, for low voltage, high
current and high frequency applications. The structures may be used in normally-on
(e.g., depletion mode) or normally-off modes. The structures include an oxide layer
positioned under the gate region which effectively reduces the junction capacitance
(gate to drain) of the structure. For normally off modes, the structures reduce
gate current at Vg in forward bias. In one embodiment, a silicide is positioned
in part of the gate to reduce gate resistance. The structures are also characterized
in that they have a thin gate due to the dipping of the spacer oxide, which can
be below 1000 angstroms and this results in fast switching speeds for high frequency applications.
