A build-up structure for chip to chip interconnects and System-In-Package utilizing
multi-angle vias for electrical and optical routing or bussing of electronic information
and controlled CTE dielectrics including mesocomposites to achieve optimum electrical
and optical performance of monolithic structures. Die, multiple die, Microelectromechanical
Machines (MEMs) and/or other active or passive components such as transducers or
capacitors can be accurately positioned on a substrate such as a copper heatsink
and multi-angle stud bumps can be placed on the active sites of the components.
A first dielectric layer is preferably placed on the components, thereby embedding
the components in the structure. Through various processes of photolithography,
laser machining, soft lithography or anisotropic conductive film bonding, escape
routing and circuitry is formed on the first metal layer. Additional dielectric
layers and metal circuitry are formed utilizing multi-angle vias to form escape
routing from tight pitch bond pads on the die to other active and passive components.
Multi-angle vias can carry electrical or optical information in the form of digital
or analog electromagnetic current, or in the form of visible or non-visible optical
bussing and interconnections.
