A cache is configured to select a cache block for eviction in response to detecting
a cache miss. The cache transmits the address of the cache block as a write transaction
on an interface to the cache, and the cache captures the address from the interface
and reads the cache block from the cache memory in response to the address. The
read may occur similar to other reads in the cache, detecting a hit in the cache
(in the cache storage location from which the cache block is being evicted). The
write transaction is initiated before the corresponding data is available for transfer,
and the use of the bus bandwidth to initiate the transaction provides an open access
time into the cache for reading the evicted cache block.
