A system for designing and implementing digital integrated circuits utilizing
a
set of synchronized sequencers that permit quick and efficient parallel processing
of system level designs. The system and method converts digital schematics and
hardware description language (HDL) based designs into a set of logic equations
and single bit arithmetic-logic operations executed by a set of parallel operating
sequencers. The system includes software for converting netlists and HDL designs
into Boolean logic equations, and a compiler for distributing these logic equations
between multiple sequencers. Each sequencer is comprised of a logic processor and
the associated program memory for storing the executable code of the assigned Boolean
logic equations and data memory for storing the results of processing of logic
equations. To synchronize execution of logic equations by multiple sequencers,
all program memories are addressed by one common address register. The processing
of logic equations is arranged in such a manner that their outputs can be read
by synchronized read instructions in the interconnected sequencers, eliminating
any need for control signals.
