System and method for testing a column redundancy of an integrated circuit memory

   
   

A system and method is disclosed for simultaneously testing columns and column redundancies of a semiconductor memory by temporarily adding an additional parallel signal bit to an input/output data bus associated therewith, the additional parallel signal bit providing greater bandwidth during test mode operation. The input/output data bus has n parallel signal bits which normally carry column data, but the additional parallel signal bit does not normally carry either column data or column redundancy data. The additional parallel signal bit may normally carry a clock signal such as an echo clock associated with the data placed on the data bus.

 
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