A method and apparatus for sensing a resistive state of a resistive memory element
includes producing a first current related to a resistance of a memory cell. The
first current is added to a second current during a first sensing time and subtracted
from a third current during a second sensing time. The first, second and third
currents are integrated over time using a capacitor, and a resulting voltage signal
on the capacitor is timed using a clocked counter. A time average value of a digital
output of the clocked counter is then related to the resistance of the memory cell,
and hence to the resistive state of the resistive memory element.
