A method for identifying and modifying, in a VLSI chip design, wire routes within
a region of wiring congestion that can be routed around that region without inducing
timing violations by the insertion and proper placement of inverters. Circuits
and nets are examined in the vicinity of the wiring congestion to determine those
nets with high potential to drive a route outside the region. Circuit locations
are analyzed to determine if the net connecting them creates a path through the
region of wiring congestion. Timing slacks are derived from the timing reports
for such nets and compared against a timing value representing the additional delay
of using an inverter pair to drive the wire route outside the region of wiring
congestion. If a net has sufficient timing slack, it is buffered with an inverter
pair which is then placed in a manner as to force the wire routes for the modified
path around the region of wiring congestion, thereby reducing the wire utilization
within the region.
