A direct memory access controller includes a source memory controller for controlling
a source memory, a destination bus controller for controlling the transfer of data
to a destination memory, a first-in-first-out memory buffer for receiving data
from the source memory, and a filter connected upstream of the first-in-first-out
memory buffer for comparing the source memory data to a filter criterion and passing
to the first-in-first-out memory buffer only that data which matches the filter criterion.
