A first gate (120) and a second gate (122) are preferably PMOS
and
NMOS transistors, respectively, formed in an n-type well (104) and a p-type
well (106). In a preferred embodiment first gate (120) includes a
first metal layer (110) of titanium nitride on a gate dielectric (108),
a second metal layer (114) of tantalum silicon nitride and a silicon containing
layer (116) of polysilicon. Second gate (122) includes second metal
layer (114) of a tantalum silicon nitride layer on the gate dielectric (108)
and a silicon containing layer (116) of polysilicon. First spacers (124)
are formed adjacent the sidewalls of the gates to protect the metals from chemistries
used to remove photoresist masks during implant steps. Since the chemistries used
are selective to polysilicon, the spacers (124) need not protect the polysilicon
capping layers, thereby increasing the process margin of the spacer etch process.
The polysilicon cap also facilitates silicidation of the gates.
