Following data writing into a memory cell array according to an internal
address signal, the data read out from each memory cell is compared with expected
value data in a readout operation. An associated memory cell array and a test block
are provided corresponding to each sub memory cell array. Each test block includes
a replacement determination unit for respective combinations of a sequence to replace
a memory cell row and a memory cell column in order. Each replacement determination
unit writes a defective address only when a defective memory cell having an address
differing from the row and column addresses of a defective memory cell already
stored is found.
