The disclosure is a non-volatile semiconductor memory device including a bias
circuit that generates a bias voltage for controlling an NMOS transistor connected
to both a bit line and a page buffer circuit. The bias circuit generates a first
voltage, which is greater than a power source voltage, as the bias signal in a
precharge period of a read operation. The bias circuit also generates a second
voltage, which is less than the power source voltage, as the bias signal in a sensing
period of the read operation.
