Semiconductor memory device having the operating voltage of the memory cell controlled

   
   

An SRAM circuit which can be operated at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

Un circuito de SRAM que se puede funcionar en un margen reducido de la operación, especialmente en un voltaje de funcionamiento bajo aumentando u optimizando el margen de la operación del circuito de SRAM. El voltaje del umbral del transistor producido en el circuito de SRAM se detecta para comparar el voltaje de funcionamiento de una célula de memoria con el voltaje de funcionamiento de un circuito periférico para ajustarlo al valor óptimo, y el voltaje de polarización del substrato se controla más a fondo.

 
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