Providing a cross point, memory array with memory plugs exhibiting a
characteristic hysteresis. The memory plugs exhibit a hysteresis that, in
the low resistive state, the first write threshold voltage is the point
above which any voltages applied across the memory plug have substantially
no effect on the resistive state and below which a voltage pulse will
alter the resistance of the memory plug. Similarly, in the high resistive
state, the second write threshold voltage is the point below which any
voltages applied across the memory plug have substantially no effect on
the resistive state and above which a voltage pulse will alter the
resistance of the memory plug. The read voltages applied to the memory
plug are typically above the first write threshold voltage and lower than
the second write threshold voltage.
